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A 700-MHZ 24-bit pipelined accumulator in 1.2-um CMOS for application as a numerically controlled oscillator

  • Fang Lu
  • Henry Samueli
  • Jiren Yuan
  • Christer Svensson
Publiceringsår: 1993
Språk: Engelska
Sidor: 878-886
Publikation/Tidskrift/Serie: IEEE Journal of Solid-State Circuits
Volym: 28
Nummer: 8
Dokumenttyp: Artikel i tidskrift
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-μm CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from DC up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7-mm×1.7-mm IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices


  • Electrical Engineering, Electronic Engineering, Information Engineering


  • ISSN: 0018-9200

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